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IDT71V546S - Synchronous SRAM

General Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Thus it has been given the name ZBTTM, or Zero Bus Turn-around.

Key Features

  • 128K x 36 memory configuration, pipelined outputs.
  • Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access).
  • ZBTTM Feature - No dead cycles between write and read cycles.
  • Internally synchronized registered outputs eliminate the need to control OE.
  • Single R/W (READ/WRITE) control pin Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ.
  • Positive clock-edge triggered address, data, and control signal registers.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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128K x 36, 3.3V Synchronous IDT71V546S SRAM with ZBT™ Feature Burst Counter and Pipelined Outputs Features ◆ 128K x 36 memory configuration, pipelined outputs ◆ Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized registered outputs eliminate the need to control OE ◆ Single R/W (READ/WRITE) control pin Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx DQ DQ ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ 4-word burst capability (interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ Single 3.