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M6MGB33BS8BWG-P - CMOS SRAM

Download the M6MGB33BS8BWG-P datasheet PDF. This datasheet also covers the M6MGT33BS8BWG-P variant, as both devices belong to the same cmos sram family and are provided as variant models within a single manufacturer datasheet.

Description

The M6MGB/T33BS8BWG-P is a Stacked Chip Scale Package (S-CSP) that contents 32M-bit Flash memory and 8M-bit SRAM in a 66-pin Stacked CSP with leaded solder ball.

Features

  • Access Time Flash SRAM 70ns (Max. ) 85ns (Max. ) F-VCC =VCC=2.7 ~ 3.0V Ta=-40 ~ 85 °C 66 pin S-CSP Ball pitch 0.80mm Outer-ball: Sn - Pb Supply Voltage Ambient Temperature Package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M6MGT33BS8BWG-P_Renesas.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Renesas

Part Number Description
M6MGB33BS8BWG CMOS SRAM
M6MGB33BS8AWG-P CMOS SRAM
M6MGB331S4BKT CMOS SRAM
M6MGB331S8AKT CMOS SRAM
M6MGB331S8BKT CMOS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com Preliminary Notice: This is not a final specification. Some parametric limits are subject to change. Renesas LSIs M6MGB/T33BS8BWG-P 33,554,432-BIT (2,097,152-WORD BY 16-BIT) CMOS FLASH MEMORY 8,388,608-BIT (524,288-WORD BY 16-BIT) CMOS SRAM Stacked-CSP (Chip Scale Package) & Description The M6MGB/T33BS8BWG-P is a Stacked Chip Scale Package (S-CSP) that contents 32M-bit Flash memory and 8M-bit SRAM in a 66-pin Stacked CSP with leaded solder ball. 32M-bit Flash memory is a 2,097,152 words, single power supply and high performance non-volatile memory fabricated by CMOS technology for the peripheral circuit and DINOR (Divided bit-line NOR) architecture for the memory cell. All memory blocks are locked and can not be programmed or erased, when F-WP# is Low.
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