* Power Supply z 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
* Clock z Fast clock cycle time for high bandwidth z Two input clocks (K and /K) for precise DDR timing at clock rising edges only z Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems z Cl
R1QGA4418RBG Datasheet (922.69 KB)
R1QGA4418RBG
922.69 KB
Sram.
Datasheet R1QGA4436RBG,R1QGA4418RBG 144-Mbit QDR™II+ SRAM 4-word Burst Architecture (2.0 Cycle Read latency) R10DS0139EJ0201 Rev.2.01 Aug 01, 2014 .
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