R1QLA4418RBG Datasheet | Renesas

R1QLA4436RBG, R1QLA4418RBG 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT R10DS0144EJ0200 Rev.2.00 Aug 01, 2014 Description The R1QLA4436RBG is a 4,194,304-word by 36-bit and the R1QLA4418RBG is a 8,388,608-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package. Features - Power Supply z 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ) - Clock z z z z Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with μs restart - I/O z z z z z z mon data input/output bus Pipelined double data rate operation HSTL I/O User programmable output impedance PLL circuitry for wide output data valid window and future frequency scaling Data valid pin (QVLD) to indicate valid data on the output - Function z Two-tick burst for low DDR transaction size z Internally self-timed write control z Simple control logic for easy depth expansion z JTAG 1149.1 patible test access port - Package z 165 FBGA package (15 x 17 x 1.4 mm) R10DS0144EJ0200 Rev.2.00 Aug 01, 2014 Page 1 of 30 R1QLA4436RBG, R1QLA4418RBG Part Number Definition Column No. 0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16 Example R 1QLA 4 4 3 6 RBG - 2 5 I B 0 The above part number is just example for 144M DDRII+ B2 x36 400MHz, 15x17mm PKG, Pb-free part. No. 0-1 2-3 Note1: Note2: Note3: Note4: - ments R1...