* Power Supply z 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
* Clock z z z z Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
R1QLA4418RBG Datasheet (947.74 KB)
R1QLA4418RBG
947.74 KB
144-mbit ddrii+ sram 2-word burst architecture.
Datasheet R1QLA4436RBG, R1QLA4418RBG 144-Mbit DDR™II+ SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT R10DS0144EJ0200 Rev.2.00 Aug .
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