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R5F11EF8AFP - MCU

This page provides the datasheet information for the R5F11EF8AFP, a member of the R5F11EFAAFP MCU family.

Features

  • Ultra-low power consumption technology.
  • VDD = single power supply voltage of 2.7 to 5.5 V.
  • HALT mode.
  • STOP mode.
  • SNOOZE mode RL78 CPU core.
  • CISC architecture with 3-stage pipeline.
  • Minimum instruction execution time: Can be changed from high-speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator) to low-speed (1.0 μs: @1 MHz operation with high-speed on-chip oscillator).
  • Multiply/divide/multiply & accumulate instruc.

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Full PDF Text Transcription

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RL78/G1G RENESAS MCU 1. OUTLINE 1.1 Features Ultra-low power consumption technology • VDD = single power supply voltage of 2.7 to 5.5 V • HALT mode • STOP mode • SNOOZE mode RL78 CPU core • CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed from high-speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator) to low-speed (1.0 μs: @1 MHz operation with high-speed on-chip oscillator) • Multiply/divide/multiply & accumulate instructions are supported. • Address space: 1 MB • General-purpose registers: (8-bit register × 8) × 4 banks • On-chip RAM: 1.
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