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Renesas Electronics Components Datasheet

R5F52205BGFP Datasheet

32-MHz 32-bit RX MCUs

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Datasheet
RX220 Group
Renesas MCUs
32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory,
12-bit A/D, ELC, MPC, IrDA, RTC, up to 7 comms channels;
incorporating functions for IEC60730 compliance
R01DS0130EJ0110
Rev.1.10
Dec 20, 2013
Features
32-bit RX CPU core
Max. operating frequency: 32 MHz
Capable of 49 DMIPS in operation at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Low-power design and architecture
Operation from a single 1.62-V to 5.5-V supply
1.62-V operation available (at up to 8 MHz)
Three low-power modes
On-chip flash memory for code, no wait states
32-MHz operation, 31.25-ns read cycle
No wait states for reading at full CPU speed
Up to 256-Kbyte capacity
User code programmable via the SCI
Programmable at 1.62 V
For instructions and operands
On-chip data flash memory
8 Kbytes (Number of times of reprogramming: 100,000)
Erasing and programming impose no load on the CPU.
On-chip SRAM, no wait states
Up to 16-Kbyte size capacity
DMA
DMAC: Incorporates four channels
DTC: Four transfer modes
ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
Reset and supply management
Seven types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
On-chip low- and high-speed oscillators, dedicated on-
chip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Year and month display or 32-bit second display (binary
counter) is selectable
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5-mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8-mm pitch
Independent watchdog timer
125-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock-frequency
accuracy-measurement circuit, independent watchdog
timer, functions to assist in RAM testing, etc.
Up to seven communications channels
SCI with many useful functions (up to five channels)
Asynchronous mode, clock synchronous mode, smart
card interface mode
IrDA Interface (one channel, in cooperation with the
SCI5)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI (one channel)
Up to 14 extended-function timers
16-bit MTU: input capture, output capture,
complementary PWM output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
12-bit A/D converter
Capable of conversion within 1.56 μs
Self-diagnostic function and analog input disconnection
detection assistance function
Analog comparator
General I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
MPC
Multiple locations are selectable for I/O pins of
peripheral functions
Operating temp. range
 40C to +85C
 40C to +105C
Page 1 of 105


Renesas Electronics Components Datasheet

R5F52205BGFP Datasheet

32-MHz 32-bit RX MCUs

No Preview Available !

RX220 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1 / 3)
Classification
CPU
Module/Function
CPU
Memory
ROM
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Reset
Voltage detection Voltage detection circuit
(LVDAa)
Low power
consumption
Interrupt
Low power consumption
facilities
Function for lower
operating power
consumption
Interrupt controller (ICUb)
Description
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Capacity: 32 K/64 K/128 K/256 Kbytes
32 MHz, no-wait memory access
On-board programming: 3 types
Capacity: 4 K/8 K/16 Kbytes
32 MHz, no-wait memory access
E2 DataFlash capacity: 8 Kbytes
Single-chip mode
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
and IWDT-dedicated on-chip oscillator
Oscillation stop detection
Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and flashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at
max.)
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
Module stop function
Three low power consumption modes
Sleep mode, all-module clock stop mode, and software standby mode
Four operating power control modes
Middle-speed operating mode 1A, middle-speed operating mode 1B, low-speed operating mode 1,
low-speed operating mode 2
Interrupt vectors: 106
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 5 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
16 levels specifiable for the order of priority
R01DS0130EJ0110 Rev.1.10
Dec 20, 2013
Page 2 of 105


Part Number R5F52205BGFP
Description 32-MHz 32-bit RX MCUs
Maker Renesas
Total Page 30 Pages
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