Datasheet Summary
R9A02G020 ASSP EASY for motor control based on RISC-V
R01DS0396EJ0110 Rev.1.10
Apr 15, 2022
Ultra low power 32 MHz RISC-V Andes N22 core, 48-KB code flash memory, 16 KB SRAM, 12-bit A/D Converter, and Safety
Features
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Features
- RISC-V Andes N22 Core
- RISC-V instruction-set architecture (RV32I)
- Maximum operating frequency: 32 MHz
- Andes Physical Memory Protection unit (Andes PMP)
- Debug and Trace: RISC-V External Debug Support
- Debug Port: JTAG
- Memory
- 48-KB code flash memory
- 16 KB SRAM
- Memory protection units
- 128-bit unique ID
- Connectivity
- Serial munications Interface (SCI) × 1
- Asynchronous interfaces
- 8-bit clock synchronous interface
- Simple IIC
-...