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R9A02G021 - 32-Bit MCU

General Description

Maximum operating frequency: up to 48 MHz Instruction-set architecture (ISA) RISC-V RV32I base integer instruction set RISC-V C standard extension for compressed instructions RISC-V M standard extension for integer multiplication and division RISC-

Key Features

  • Features.
  • RISC-V Core.
  • Renesas RISC-V instruction-set architecture (RV32I [MACB]).
  • Maximum operating frequency: 48 MHz.
  • Debug and Trace: RISC-V External Debug Support.
  • Debug Port: cJTAG.
  • 32-pin HWQFN (5 mm × 5 mm, 0.5 mm pitch).
  • 24-pin HWQFN (4 mm × 4 mm, 0.5 mm pitch).
  • 16-pin WLCSP(1.99 mm × 1.99 mm, 0.4 mm pitch).
  • Memory.
  • 128-KB code flash memory.
  • 4 KB data flash.
  • 16 KB SRAM.
  • 128-bit unique ID.
  • Connectivity.

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Datasheet R9A02G021 32-Bit MCU based on RISC-V R01DS0422EJ0110 Rev.1.10 Feb 29, 2024 Ultra low power 48 MHz Renesas RISC-V core with 128-KB code flash memory, 16 KB SRAM, 12-bit A/D Converter, and Safety features. Features ■ RISC-V Core ● Renesas RISC-V instruction-set architecture (RV32I [MACB]) ● Maximum operating frequency: 48 MHz ● Debug and Trace: RISC-V External Debug Support ● Debug Port: cJTAG – 32-pin HWQFN (5 mm × 5 mm, 0.5 mm pitch) – 24-pin HWQFN (4 mm × 4 mm, 0.5 mm pitch) – 16-pin WLCSP(1.99 mm × 1.99 mm, 0.