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R9A02G020 - ASSP EASY

General Description

Maximum operating frequency: up to 32 MHz Andes AndesCore N22: Revision: 1.4.1 RISC-V instruction-set architecture (ISA) RISC-V RV32I base integer instruction set RISC-V RVC standard extension for compressed instructions RISC-V RVM standa

Key Features

  • Features.
  • RISC-V Andes N22 Core.
  • RISC-V instruction-set architecture (RV32I).
  • Maximum operating frequency: 32 MHz.
  • Andes Physical Memory Protection unit (Andes PMP).
  • Debug and Trace: RISC-V External Debug Support.
  • Debug Port: JTAG.
  • Memory.
  • 48-KB code flash memory.
  • 16 KB SRAM.
  • Memory protection units.
  • 128-bit unique ID.
  • Connectivity.
  • Serial Communications Interface (SCI) × 1.
  • Asynchronous interfaces.
  • 8-bit clock.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Datasheet R9A02G020 ASSP EASY for motor control based on RISC-V R01DS0396EJ0110 Rev.1.10 Apr 15, 2022 Ultra low power 32 MHz RISC-V Andes N22 core, 48-KB code flash memory, 16 KB SRAM, 12-bit A/D Converter, and Safety features.