RC22504A Datasheet, Renesas

* Jitter as low as 64 fs RMS maximum (10Hz to 20MHz)
* PLL core consists of fractional-feedback Analog PLL (APLL) ○ Operates from a 25MHz to 80MHz crystal or XO ○.

The device is a member of Renesas' highperformance FemtoClock2 family. Applications
* Reference clock generator for.

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