UPD48011318 Description
The μPD48011318 is a 67,108,864-word by 18-bit and the μPD48011336 is a 33,554,432-word by 36-bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor eDRAM memory cell. The Low Latency DRAM-III chip is a 1.1Gbit DRAM capable of a sustained throughput of approximately 43.2 Gbps for burst length of 2 (approximately 51.2 Gbps for applications implementing error...
UPD48011318 Key Features
- 1 cycle 600MHz DDR Muxed Address
- Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power
- Training sequence for per-bit deskew
- Selectable Refresh Mode: Auto or Overlapped Refresh
- Programmable PVT-pensated output impedance
- Programmable PVT-pensated on-die input termination
- PLL for improved input jitter tolerance and wide output data valid window