Datasheet4U Logo Datasheet4U.com

UPD48011318 Datasheet Low Latency DRAM

Manufacturer: Renesas

📥 Download Datasheet

General Description

The μPD48011318 is a 67,108,864-word by 18-bit and the μPD48011336 is a 33,554,432-word by 36-bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor eDRAM memory cell.

The Low Latency DRAM-III chip is a 1.1Gbit DRAM capable of a sustained throughput of approximately 43.2 Gbps for burst length of 2 (approximately 51.2 Gbps for applications implementing error correction), excluding refresh overhead and data bus turn-around With a bus speed of 600 MHz, a burst length of 2, and a tRC of 13.3 ns, the Low Latency DRAM-III chip is capable of achieving this rate when accesses to at least 6 banks of memory are overlapped.

These products are packaged in 180-pin TAPE FBGA.

Overview

μPD48011318 μPD48011336 1.1G-BIT Low Latency DRAM-III Common I/O Burst Length of 2 Datasheet R10DS0012EJ0200 Rev.2.

Key Features

  • 1 cycle 600MHz DDR Muxed Address.
  • Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power.
  • Training sequence for per-bit deskew.
  • Selectable Refresh Mode: Auto or Overlapped Refresh.
  • Programmable PVT-compensated output impedance.
  • Programmable PVT-compensated on-die input termination.
  • PLL for improved input jitter tolerance and wide output data valid window Ordering Information Part number Cycle C.

More Datasheets from Renesas

Part Number Description
UPD48011336 Low Latency DRAM
uPD44325092B 36M-BIT QDR II SRAM
uPD44325182B 36M-BIT QDR II SRAM
uPD44325362B 36M-BIT QDR II SRAM
uPD46184095B 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
uPD46184182B 18M-BIT DDR II SRAM 2-WORD BURST OPERATION
uPD46184184B 18M-BIT DDR II SRAM 4-WORD BURST OPERATION
uPD46184185B 18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
uPD46184362B 18M-BIT DDR II SRAM 2-WORD BURST OPERATION
uPD46185084B 18M-BIT QDR II SRAM 4-WORD BURST OPERATION