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Renesas Electronics Components Datasheet

UPD48011336 Datasheet

Low Latency DRAM

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μPD48011318
μPD48011336
1.1G-BIT Low Latency DRAM-III
Common I/O Burst Length of 2
Datasheet
R10DS0012EJ0200
Rev.2.00
Feb 01, 2013
Description
The μPD48011318 is a 67,108,864-word by 18-bit and the μPD48011336 is a 33,554,432-word by 36-bit synchronous
double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor eDRAM memory cell.
The Low Latency DRAM-III chip is a 1.1Gbit DRAM capable of a sustained throughput of approximately 43.2 Gbps for
burst length of 2 (approximately 51.2 Gbps for applications implementing error correction), excluding refresh overhead
and data bus turn-around
With a bus speed of 600 MHz, a burst length of 2, and a tRC of 13.3 ns, the Low Latency DRAM-III chip is capable of
achieving this rate when accesses to at least 6 banks of memory are overlapped.
These products are packaged in 180-pin TAPE FBGA.
Specification
Density: 1,1Gbit
Organization: 8M words x 18 bits x 8 banks
4M words x 36 bits x 8 banks
Operating frequency
600MHz (MAX.) @ tRC=13.3 ns
tRC
13.3 ns tRC ( and 13.3 ns tRFC )
Burst length: 2
Address bus
1 cycle DDR address
Package
180-pin FBGA (Ball Array: 1 mm x 1 mm Pitch)
Package size: 18.5 mm x 14 mm
ROHS 6/6 compliance
Power supply
- 2.5 V VEXT
- 1.5 V VDD
- 1.0 V VDDQ
Refresh command
- Auto Refresh : 16384 cycles / 2 ms for each bank
- Overlapped Refresh with DPR# pin
Operating case temperature: 0 to 95 °C
R10DS0012EJ0200 Rev.2.00
Feb 01, 2013
Page 1 of 50


Renesas Electronics Components Datasheet

UPD48011336 Datasheet

Low Latency DRAM

No Preview Available !

μPD48011318, μPD48011336
Features
1 cycle 600MHz DDR Muxed Address
Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power
Training sequence for per-bit deskew
Selectable Refresh Mode: Auto or Overlapped Refresh
Programmable PVT-compensated output impedance
Programmable PVT-compensated on-die input termination
PLL for improved input jitter tolerance and wide output data valid window
Ordering Information
Part number
Cycle Clock Random Output Supply Burst Address Organization Package
Time Frequency Cycle
Voltage Length Type (word x bit)
(VDDQ)
ns
MHz
ns
V
μPD48011318FF-FH16-FF1-A 1.66
600
13.3
1.0
2
DDR
64 M x 18
180-pin
μPD48011318FF-FH19-FF1-A 1.90
525
TAPE FBGA
μPD48011336FF-FH16-FF1-A 1.66
600
32 M x 36 (18.5 x14)
μPD48011336FF-FH19-FF1-A 1.90
525
Lead-free
R10DS0012EJ0200 Rev.2.00
Feb 01, 2013
Page 2 of 50



Part Number UPD48011336
Description Low Latency DRAM
Maker Renesas
Total Page 3 Pages
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