BL1302A57S Datasheet | SHANGHAI BELLING

BL1302A57/S General Description The BL1302A57/S is an A-law monolithic PCM Pin Assignment CODEC/filter which has the A/D and D/A conversion and a serial PCM interface. The device is fabricated using the advanced double-poly nwell CMOS process. It is pin patible with TP3057. The encode portion of each device consists of an input gain adjust amplifier, an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz. Also included are auto-zero circuitry and a VBB GNDA VFRO VCC FSR DR BCLKR/CLKSEL MCLKR/PDN 1 2 3 4 5 6 7 8 BL1302A57 16 VFXI+ 15 VFXI14 GSX 13 TSX 12 FS X 11 DX 10 BCLKX 9 MCLKX panding coder which samples the filtered signal and encodes it in the panded A-law PCM format. The decode portion consists of an expanding decoder, which reconstructs the Analog signal from the panded A-law code, a low-pass filter which corrects for the sinx/x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads. The device requires two 1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive master clocks, which may be asynchronous; transmit and receive bit clocks , which may vary from 64 KHz to 2.048 MHz; and transmit and receive frame sync pulses. The timing of the frame sync pulses and PCM data is patible with both industry standard formats. . Features - plete CODEC and filtering system (BO) including: --- Transmit high-pass and low-pass filtering --- Receive low-pass filter with sinx/x correction --- Active RC noise filters --- A-law patible COder and DECoder --- Internal precision voltage reference --- Serial I/O interface --- Internal auto-zero circuitry - 16 pin DIP or SOP - Designed for ITU application http://.belling..cn -1- Total 17 Pages 8/28/2006 Wrote by...