74HC699 Datasheet | STMicroelectronics

M54/74HC696/697 M54/74HC698/699 HC696/698 U/D DECADE COUNTER/REGISTER (3-STATE) HC697/699 U/D 4 BIT BINARY COUNTER/REGISTER (3-STATE) - . . . HIGH SPEED f MAX = 50 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS (for QA to QD) 10 LSTTL LOADS (for RCO) SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 6 m A (MIN.) FOR QA TO QD |IOH| = IOL = 4 m A (MIN.) FOR RCO OUTPUT BALANCED PROPAGATION DELAYS t PLH = t PHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION PATIBLE WITH LSTTL 54/74LS696/697/698/699 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R DESCRIPTION The HC696/697 are high speed CMOS up/down counters fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The HC696/698 are BCD DECADE COUNTER, and the HC697/699 are 4-BIT BINARY COUNTER. Both devices have register. They count on the positive edge of the counter clock input (CCK) when selected by the ”Counter Mode”. If the input U/D is held ”H”, the internal counter counts up, and held ”L”, counts down. The internal counter’s outputs are stored in the output register at the positive edge of register clock (RCK). The counter Features enable P and enable T and a ripple-carry output for easy expansion. the register/counter select input, R/C, selects the counter when low or the register when high for the three state outputs, QA, QB, Qc and QD. Both the counter clock CCK and register clock RCK are positive-edge triggered. The counter clear CCLR is active low and is synchronous for HC698/699, and asynchronous for HC696/697. All inputs are equipped with protection circuits against static discharge and transient excess voltage. March 1993 PIN CONNECTIONS (top view) NC = No...