74LCX125
Features
- 5 V tolerant inputs and outputs
- High speed
- t PD = 5.2 ns (max.) at VCC = 3 V
- Power-down protection on inputs and outputs
- Symmetrical output impedance
- |IOH| = IOL = 24 m A (min.) at VCC = 3 V
- PCI bus levels guaranteed at 24 m A
- Balanced propagation delay
- t PLH ≅ t PHL
- Operating voltage range
- VCC (opr.) = 2.0 V to 3.6 V
- Pin and function patible with 74 series 125
- Latch-up performance exceeds 500 m A
(JESD 17)
- ESD performance
- HBM: 2000 V (MIL STD 883 method 3015)
- MM: 200 V
- CDM: 1000 V
Applications
- Automotive
- Industrial
- puter
- Consumer
TSSOP14
SO-14
Description
The 74LCX125 device is a low-voltage CMOS quad bus buffer manufactured with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low-power and highspeed 3.3 V applications and can be interfaced to a 5 V signal environment for both inputs and outputs.
The device requires the 3-state control input G to be set high to place the output in the high...
