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IMSA110
IMAGE AND SIGNAL PROCESSING SUB–SYSTEM
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1-D/2-D SOFTWARE CONFIGURABLE CONVOLVER/FILTER ON-CHIP PROGRAMMABLE LINE DELAYS (0 — 1120 STAGES) 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE 21 MULTIPLY-AND-ACCUMULATE STAGES 1-D (21) OR 2-D (3 x 7) CONVOLUTION WINDOW ON-CHIP POST PROCESSOR FOR DATA TRANSFORMATION FULLY CASCADABLE IN WINDOW SIZE AND ACCURACY 20 MHZ DATA THROUGHPUT (420 MOPS) SIGNED/UNSIGNED DATA AND COEFFICIENTS MICROPROCESSOR INTERFACE HIGH SPEED CMOS IMPLEMENTATION TTL COMPATIBLE SINGLE +5V ± 10% SUPPLY POWER DISSIPATION < 2.0 WATTS 100 PIN CERAMIC PGA
PGA100 (Ceramic Grid Array Package)
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IMSA110 Datasheet
