M54HC147 Datasheet | STMicroelectronics

M54HC147 M74HC147 10 TO 4 LINE PRIORITY ENCODER - . . . HIGH SPEED t PD = 15 ns (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 m A (MIN.) BALANCED PROPAGATION DELAYS t PLH = t PHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION PATIBLE WITH 54/74LS147 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC147F1R M74HC147M1R M74HC147B1R M74HC147C1R DESCRIPTION The M54/74HC147 is a high speed CMOS 10 TO 4 LINE PRIORITY ENCODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL bined with true CMOS low power consumption. This device Features priority encoding of the inputs to ensure that only the highest order data line is encoded. Nine input lines are encoded to a four line BCD output. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are at high logic level. All data input and outputs are active at the low logic level. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/10 M54/M74HC147 TRUTH TABLE INPUTS 1 H X X X X X X X X L X: Don’t Care OUTPUTS 6 H X X X L H H H H H 7 H X X L H H H H H H 8 H X L H H H H H H H 9 H L H H H H H H H H D H L L H H H H H H H C H H H L L L L H H H B H H H L L H H L L H A H L H L H L H L H L 2 H X X X X X X X L H 3 H X X X X X X L H H 4 H X X X X X L H H H 5 H X X X X L H H H H LOGIC DIAGRAM 2/10 M54/M74HC147 PIN DESCRIPTION PIN No 9, 7, 6, 14 11, 12, 13, 1, 2, 3, 4, 5, 10 15 8 16 SYMBOL A to D 1 to 9 NAME AND FUNCTION BCD Address Outputs (Active LOW) Decimal Data Inputs (Active LOW) Not Connected Ground (0V) Positive Supply...