* individual J,K, clock, and asynchronous set and clearinputs for each flip-flop. When the clock goes high, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is high and the bistable will function as shown in the truth
M54HC112 Datasheet (251.26 KB)
M54HC112
251.26 KB
Dual j-k flip flop.
M54HC112 M74HC112
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
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HIGH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = .
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