M68Z128W Datasheet | STMicroelectronics

DESCRIPTION The M68Z128W is a 1 Mbit (1,048,576 bit) Fast CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3.0V (+0.6V / - 0.3V) supply, and all inputs and outputs are TTL patible. This device has an automatic power-down feature , reducing the power consumption by over 99% when deselected. The M68Z128W is available in the standard 450mil-wide TSOP type 1 package. Figure 1. Logic Diagram 17 A0-A16 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC Address Inputs Data Input/Output Chip Enable 1 Chip Enable 2 Output Enable Write Enable W E1 E2 G M68Z128W Supply Voltage Ground Not Connected Internally AI01878B March 2000 1/12 Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG VIO (2) VCC IO (3) PD Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltage Supply Voltage Output Current Power Dissipation Value 0 to 70 - 65 to 150 - 0.5 to VCC + 0.5 - 0.5 to 4.6 20 1 Unit °C °C V V m A W Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Up to a maximum operating VCC of 3.6V only. 3. One output at a time, not to exceed 1 second duration. Figure 2. TSOP Connections A11 A9 A8 A13 W E2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 8 9 25 24 AI00698B G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 the 1,048,576 locations in the static memory array,...