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SPC58NE84H0 - 32-bit Power Architecture microcontroller

Download the SPC58NE84H0 datasheet PDF. This datasheet also covers the SPC58EE80E7 variant, as both devices belong to the same 32-bit power architecture microcontroller family and are provided as variant models within a single manufacturer datasheet.

General Description

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Key Features

  • AEC-Q100 qualified.
  • 32-bit Power Architecture VLE compliant CPU cores:.
  • Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), two of them having one checker core in lock-step.
  • Floating Point, End-to-End Error Correction.
  • 6576 KB (6288 KB code flash + 288 KB data flash) on-chip flash memory:.
  • supports read during program and erase operations, and multiple blocks allowing EEPROM emulation.
  • Supports read while read between t.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SPC58EE80E7-STMicroelectronics.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by STMicroelectronics

Part Number Description
SPC58NE84C3 32-bit Power Architecture microcontroller
SPC58NE84C3 32-bit Power Architecture microcontroller
SPC58NE84E7 32-bit Power Architecture microcontroller
SPC58NE84E7 32-bit Power Architecture microcontroller
SPC58NE80C3 32-bit Power Architecture microcontroller

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SPC58EEx, SPC58NEx 32-bit Power Architecture® microcontroller for automotive ASIL-D applications Datasheet - production data FPBGA292 (17 x 17 x 1.8 mm) eLQFP176 (24 x 24 x 1.4 mm) Known Good Die Features • AEC-Q100 qualified • 32-bit Power Architecture VLE compliant CPU cores: – Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), two of them having one checker core in lock-step – Floating Point, End-to-End Error Correction • 6576 KB (6288 KB code flash + 288 KB data flash) on-chip flash memory: – supports read during program and erase operations, and multiple blocks allowing EEPROM emulation – Supports read while read between the two code Flash partitions.