ST20TP2BX50S ic equivalent, programmable transport ic.
s Enhanced 32-bit VL-RISC CPU 0 to 50 MHz processor clock fast integer/bit operations very high code density s 8 Kbytes on-chip SRAM 200 Mbytes/s maximum bandwidth s Prog.
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FEATURES s Enhanced 32-bit VL-RISC CPU 0 to 50 MHz processor clock fast integer/bit operations very high code density .
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12 Clocks and low power controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
12.1 12.2 12.3 12.4 Clocks ..... Low power control ....... Low power configuration registers .. Clocking .. 83 83 85 88
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