STL30NF3LL
DESCRIPTION
This Power MOSFET is the second generation of STMicroelectronics unique “STrip FET™” technology. The resulting transistor shows extremely low onresistance and minimal gate charge. The new Power FLAT™ package allows a significant reduction in board space without promising performance.
Power FLAT™(6x5) (Chip Scale Package)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS s DC-DC CONVERTERS s BATTERY MANAGEMENT IN NOMADIC EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol VDS VDGR VGS ID(#) IDM (l) PTOT Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Storage Temperature Max. Operating Junction Temperature Value 30 30 ± 16 30 19 120 80 0.64
- 55 to 150 Unit V V V A A A W W/°C °C
(q) Pulse width limited by safe operating area (#) Limited by Wire Bonding
November 2001
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