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K3N4C1000D-GC - 8M-Bit CMOS Mask ROM

Download the K3N4C1000D-GC datasheet PDF. This datasheet also covers the K3N4C1000D-DC variant, as both devices belong to the same 8m-bit cmos mask rom family and are provided as variant models within a single manufacturer datasheet.

Description

The K3N4C1000D-D(G)C is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1,048,576 x 8 bit(byte mode) or as 524,288 x16 bit(word mode) depending on BHE voltage level.

Features

  • Switchable organization 1,048,576 x 8(byte mode) 524,288 x 16(word mode).
  • Fast access time : 100ns(Max. ).
  • Supply voltage : single +5V.
  • Current consumption Operating : 50mA(Max. ) Standby : 50µA(Max. ).
  • Fully static operation.
  • All inputs and outputs TTL compatible.
  • Three state outputs.
  • Package -. K3N4C1000D-DC : 42-DIP-600 -. K3N4C1000D-GC : 44-SOP-600 CMOS MASK ROM.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K3N4C1000D-DC_SamsungElectronics.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number K3N4C1000D-GC
Manufacturer Samsung Electronics
File Size 61.69 KB
Description 8M-Bit CMOS Mask ROM
Datasheet download datasheet K3N4C1000D-GC Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K3N4C1000D-D(G)C 8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM FEATURES • Switchable organization 1,048,576 x 8(byte mode) 524,288 x 16(word mode) • Fast access time : 100ns(Max.) • Supply voltage : single +5V • Current consumption Operating : 50mA(Max.) Standby : 50µA(Max.) • Fully static operation • All inputs and outputs TTL compatible • Three state outputs • Package -. K3N4C1000D-DC : 42-DIP-600 -. K3N4C1000D-GC : 44-SOP-600 CMOS MASK ROM GENERAL DESCRIPTION The K3N4C1000D-D(G)C is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1,048,576 x 8 bit(byte mode) or as 524,288 x16 bit(word mode) depending on BHE voltage level.
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