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KM641001B - CMOS SRAM

Description

The KM641001B is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits.

The KM641001B/BL uses 4 common input and output lines and has at output enable pin which operates faster than address access time at read cycle.

Features

  • Fast Access Time 15, 20ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 20mA(Max. ) (CMOS) : 5mA(Max. ) 1mA(Max) L-Ver. Only Operating KM641001B/BL - 15 : 120mA(Max. ) KM641001B/BL - 20 : 118mA(Max. ).
  • Single 5.0V±10% Power Supply.
  • TTL Compatible Inputs and Outputs.
  • Fully Static Operation - No Clock or Refresh required.
  • Three State Outputs.
  • 2V Minimum Data Retention ; L-Ver. only.
  • Standard Pin Configuration KM641001B/BLJ : 28-SO.

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Other Datasheets by Samsung Semiconductor

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Full PDF Text Transcription

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www.DataSheet4U.com PRELIMINARY CMOS SRAM KM641001B/BL Document Title 256Kx4 Bit (with OE) High Speed Static RAM(5V Operating), Evolutionary Pin out. Revision History Rev. No. Rev. 0.0 Rev.1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete 17ns, L-version and Industrial Temperature Part. 2.3. Delete VOH1=3.95V. 2.4. Delete Data Retention Characteristics and Wave form. 2.5. Relex operating current. Speed Previous Now 15ns 120mA 120mA 17ns 110mA 20ns 100mA 118mA 3.1. Add Low power Version. 3.2. Add Data Retention chcracteristics. Draft Data Feb. 1st 1997 Jun. 1st 1997 Remark Design Target Preliminary Rev. 2.0 Feb. 6th 1998 Final Rev.3.0 Jul.
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