* 200MHz Clock, 400Mbps data rate.
* VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V
* Double-data-rate architecture; two data transfers per clock cycle
* Bidirectional data strobe(DQS)
* Four banks operation
* Differential clock inputs(CK and CK)
* DL
K4H561638F-UCC4 Datasheet (171.36 KB)
K4H561638F-UCC4
Samsung semiconductor
171.36 KB
256mb f-die ddr400 sdram.
DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM 256Mb F-die DDR400 SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Revision 1.1 Rev. 1.1 Au.
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