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* Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-.

GW, BW, LBO, ZZ. Write cycles are internally self-timed and synchronous. Full bus-width write is done by GW, and each b.

The K7A203200A is a 2,097,152-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 64K words of 32bits and integrates address and control registers, a 2-.

K7A203200B

K7A203600A

K7A203600B

K7A201800B

K7A161800A

K7A161801A

K7A161830B

K7A161831B

K7A163200A

K7A163201A

K7A163600A

K7A163601A

K7A163630B