K7A203200A
FEATURES
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- Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. Self-Timed Write Cycle. On-Chip Address and Control Registers. VDD= 3.3V+0.3V/-0.165V Power Supply. VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. 5V Tolerant Inputs Except I/O Pins. Byte Writable Function. Global Write Enable Controls a full bus-width write. Power Down State via ZZ Signal. LBO Pin allows a choice of either a interleaved burst or a linear burst. Three Chip Enables for simple depth expansion with No Data Contention ; 2 cycle Enable, 1 cycle Disable. Asynchronous Output Enable Control. ADSP, ADSC, ADV Burst Control Pins. TTL-Level Three-State Output. 100-TQFP-1420A
64Kx32 Synchronous SRAM
64Kx32-Bit Synchronous Pipelined Burst SRAM
GENERAL DESCRIPTION
The K7A203200A is a 2,097,152-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC...
