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K7A801809A Datasheet 256Kx36 & 512Kx18 Synchronous SRAM

Manufacturer: Samsung Semiconductor

Overview: K7A803609A K7A801809A Document Title 256Kx36 & 512Kx18 Synchronous SRAM 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 1.0 History Initial draft 1. Final spec Release. Draft Date May. 24 . 2000 July. 03. 2000 Remark Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- July 2000 Rev 1.0 Free Datasheet http://www.datasheet4u.

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General Description

The K7A803609A and K7A801809A are 9,437,184-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

It is organized as 256K(512K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for

Key Features

  • Synchronous Operation.
  • 2 Stage Pipelined operation with 4 Burst.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • 3.3V+0.165V/-0.165V Power Supply.
  • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Powe.

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