Description
1.1 Added AC characteristic timing diagram (include Standby timing diagram)
Draft Date Mar, 01. 2004 May, 18. 2004
July, 15. 2004
Remark
Table of Contents
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Introduction 2 Features 2 Products 2 Block Diagram3 Pixel Array4 Chip Pad Configuration5 Chip Pad Description 6 Package
Features
- 2 Products 2 Block Diagram3 Pixel Array4 Chip Pad Configuration5 Chip Pad Description 6 Package Pin Configuration (48 CLCC, Test Only) 7 Package Pin Description (48CLCC, Test Only) 8 Maximum Absolute Limit9
Electrical Characteristics 10
Control Registers 13 Operation Description 18 Timing Chart25
Vertical Timing Diagram 25
48CLCC Package Dimension (Test Only) 29
List of Figures
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Figure Number
Title
Page Number
Figure 1. Block Diagram 3
Figure 2. Pixel Array Configuration 4
Figure 3. Pin Configuration 7
Figure 4. WOI definition 18
Figure 5. Bayer Space Sub-Sampling Examples 19
Figure 6. Relative Channel Gain 20
Figure 7. Relative Global Gain 21
Figure 8. Recommended Minimum Global Gain Control Value 21
Figure 9. Quadrisectional Global Gain Control 22
F.
