SLGSSTVF16859H Description
The 14-bit SLGSSTVF16859 is a registered buffer designed for 2.3V to 2.7V VDD operating range. Inputs are SSTL_2 levels, except for the LVCMOS RESET input. Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signal (RESET).
SLGSSTVF16859H Key Features
- patible with JEDEC standard SSTV16859
- Differential Clock inputs
- SSTL_2 data input signaling
- Supports SSTL_2 class I output specifications
- Output circuitry minimizes effects of SSO and unterminated lines
- LVCMOS input levels on RESET pin
- 2.3V-2.7V Operation for PC1600/2100/2700
- 2.5V-2.7V Operation for PC3200
- Max Clock frequency > 210MHz