SI53112 Datasheet (DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER)

Part: SI53112
Manufacturer: Silicon Laboratories
Size: 1.33 MB

SI53112 Key Features

Twelve 0.7 V low-power, push
PLL or bypass mode
Spread spectrum tolerable
1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
PLL bandwidth SW SMBUS programming overrides the latch
Gen 3 SRNS pliant
100 ps input-to-output delay
For higher output devices or

Related Silicon Laboratories Datasheets

Part Number	Description
SI53115	15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER
SI53119	19-OUTPUT PCIE GEN 3 BUFFER
SI531	CRYSTAL OSCILLATOR
SI53102-A1	FAN-OUT CLOCK BUFFER
SI53102-A2	FAN-OUT CLOCK BUFFER

SI53112 Description

The Si53112 is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and...