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SI53115 - 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER

General Description

The Si53115 is a 15-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification.

Key Features

  • Fifteen 0.7 V low-power, push-.
  • Separate VDDIO for outputs pull HCSL PCIe Gen3 outputs.
  • PLL or bypass mode.
  • 100 MHz /133 MHz PLL.
  • Spread spectrum tolerable.
  • operation, supports PCIe and QPI.
  • PLL bandwidth SW SMBUS programming overrides the latch.
  • 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) value from HW pin.
  • Low phase jitter (Intel QPI, PCIe.
  • 9 selectable SMBUS addresses Gen 1/.

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Other Datasheets by Silicon Laboratories

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Si53115 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER Features  Fifteen 0.7 V low-power, push-  Separate VDDIO for outputs pull HCSL PCIe Gen3 outputs  PLL or bypass mode  100 MHz /133 MHz PLL  Spread spectrum tolerable  operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch   1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) value from HW pin  Low phase jitter (Intel QPI, PCIe  9 selectable SMBUS addresses Gen 1/2/3/4 common clock compliant)  SMBus address configurable to allow multiple buffers in a single  Gen 3 SRNS Compliant control network 3.