SI53115 Datasheet | Silicon Labs

Features - Fifteen 0.7 V low-power, push- - Separate VDDIO for outputs pull HCSL PCIe Gen3 outputs - PLL or bypass mode - 100 MHz /133 MHz PLL - Spread spectrum tolerable - operation, supports PCIe and QPI - PLL bandwidth SW SMBUS programming overrides the latch - - 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) value from HW pin - Low phase jitter (Intel QPI, PCIe - 9 selectable SMBUS addresses Gen 1/2/3/4 mon clock pliant) - SMBus address configurable to allow multiple buffers in a single - Gen 3 SRNS pliant control network 3.3 V supply - 100 ps input-to-output delay voltage operation - Extended Temperature: - 40 to 85 °C - 64-pin QFN Ordering Information: See page 30. Pin Assignments 64 GND 63 VDD_IO 62 DIF_14 61 DIF_14 60 DIF_13 59 DIF_13 58 VDD 57 GND 56 DIF_12 55 DIF_12 54 DIF_11 53 DIF_11 52 GND 51 VDD_IO 50 DIF_10 49 DIF_10 Applications - Server - Storage - Data center - Enterprise switches and routers Description The Si53115 is a 15-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® Quick Path Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/ Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at .silabs./pcie-learningcenter. VDDA 1 GNDA 2 100M_133M 3 HBW_BYPASS_LBW 4 PWRGD / PWRDN 5 GND 6 VDDR 7 CLK_IN 8 CLK_IN 9 SA_0 10 SDA 11 SCL 12 SA_1 13 FBOUT_NC 14 FBOUT_NC 15 GND 16 Patents pending DIF_0 17 DIF_0 18 VDD_IO 19 GND 20 DIF_1 21 DIF_1 22 DIF_2 23 DIF_2 24 GND 25 VDD 26 DIF_3 27 DIF_3 28 DIF_4 29 DIF_4 30 VDD_IO...