Description
The Si53115 is a 15-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification.
Features
- Fifteen 0.7 V low-power, push-.
- Separate VDDIO for outputs
pull HCSL PCIe Gen3 outputs.
- PLL or bypass mode.
- 100 MHz /133 MHz PLL.
- Spread spectrum tolerable.
- operation, supports PCIe and QPI.
- PLL bandwidth SW SMBUS programming overrides the latch.
- 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode)
value from HW pin.
- Low phase jitter (Intel QPI, PCIe.
- 9 selectable SMBUS addresses
Gen 1/.
SI53115 Datasheet
