SI53115 Description
The Si53115 is a 15-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/ Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz...
SI53115 Key Features
- Fifteen 0.7 V low-power, push
- Separate VDDIO for outputs
- PLL or bypass mode
- 100 MHz /133 MHz PLL
- Spread spectrum tolerable
- operation, supports PCIe and QPI
- PLL bandwidth SW SMBUS programming overrides the latch
- Low phase jitter (Intel QPI, PCIe
- 9 selectable SMBUS addresses
- SMBus address configurable to allow multiple buffers in a single