SI53112 Datasheet | Silicon Labs

Features - Twelve 0.7 V low-power, push- - PLL or bypass mode pull, HCSL-patible - Spread spectrum tolerable PCIe Gen 3 outputs - 1.05 to 3.3 V I/O supply voltage - - Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, supports PCIe and QPI - - - 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 mon clock pliant) - PLL bandwidth SW SMBUS programming overrides the latch - Gen 3 SRNS pliant value from HW pin - 100 ps input-to-output delay - - 9 selectable SMBUS addresses SMBus address configurable to allow multiple buffers in a single - - Extended Temperature: - 40 to 85 °C Package: 64-pin QFN control network 3.3 V supply - For higher output devices or voltage operation variations of this device, contact Silicon Labs Ordering Information: See page 30. Patents pending Applications - Server - Storage - Datacenter - Enterprise Switches and Routers Description The Si53112 is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® Quick Path Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at .silabs./pcie-learningcenter. Rev. 1.1 12/15 Copyright © 2015 by Silicon Laboratories Functional Block Diagram OE_[11:0] 12 CLK_IN CLK_IN 100M_133...