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SI53112 - DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER

General Description

The Si53112 is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification.

Key Features

  • Twelve 0.7 V low-power, push-.
  • PLL or bypass mode pull, HCSL-compatible.
  • Spread spectrum tolerable PCIe Gen 3 outputs.
  • 1.05 to 3.3 V I/O supply voltage.
  • Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, supports PCIe and QPI.
  • 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 common clock compliant).
  • PLL bandwidth SW SMBUS programming overrides the lat.

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Other Datasheets by Silicon Laboratories

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Si53112 DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER Features  Twelve 0.7 V low-power, push-  PLL or bypass mode pull, HCSL-compatible  Spread spectrum tolerable PCIe Gen 3 outputs  1.05 to 3.3 V I/O supply voltage   Individual OE HW pins for each output clock 100 MHz /133 MHz PLL operation, supports PCIe and QPI    50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 common clock compliant)  PLL bandwidth SW SMBUS programming overrides the latch  Gen 3 SRNS Compliant value from HW pin  100 ps input-to-output delay   9 selectable SMBUS addresses SMBus address configurable to allow multiple buffers in a single   Extended Temperature: –40 to 85 °C Package: 64-pin QFN control network 3.