SI53112 Description
The Si53112 is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and...
SI53112 Key Features
- Twelve 0.7 V low-power, push
- PLL or bypass mode
- Spread spectrum tolerable
- 1.05 to 3.3 V I/O supply voltage
- 50 ps output-to-output skew
- PLL bandwidth SW SMBUS programming overrides the latch
- Gen 3 SRNS pliant
- 100 ps input-to-output delay
- For higher output devices or