Si53119 Datasheet | Skyworks Solutions

Features - Nineteen 0.7 V low-power, push- - PLL or bypass mode pull HCSL PCIe Gen 3 outputs - Spread spectrum tolerable - 100 MHz /133 MHz PLL - 1.05 to 3.3 V I/O supply voltage - operation, supports PCIe and QPI - PLL bandwidth SW SMBUS programming overrides the latch - - value from HW pin 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel QPI, PCIe Gen 1/2/3 mon clock pliant) - - 9 selectable SMBUS addresses SMBus address configurable to allow multiple buffers in a single - - Gen 3 SRNS pliant 100 ps input-to-output delay control network 3.3 V supply - Extended Temperature: voltage operation - 40 to 85 °C - Separate VDDIO for outputs - 72-pin QFN - For variations of this device, contact Skyworks Solutions Applications - Server - Storage - Data center - Enterprise switches and routers Description The Si53119 is a 19-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® Quick Path Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Skyworks Solutions PCIe Clock Jitter Tool. Download it for free at https://.skyworksinc./en/application-pages/pciexpress-learning-center. Ordering Information: See page 31. Pin Assignments 72 DIF_18 71 DIF_18 70 GND 69 VDD_IO 68 DIF_17 67 DIF_17 66 DIF_16 65 DIF_16 64 VDD 63 GND 62 DIF_15 61 DIF_15 60 DIF_14 59 DIF_14 58 GND 57 VDD_IO 56 DIF_13 55 DIF_13 DIF_1 19 DIF_1 20 VDD_IO 21 GND 22 DIF_2 23 DIF_2 24 DIF_3 25 DIF_3 26 GND 27 VDD 28 DIF_4 29 DIF_4 30 DIF_5 31 DIF_5 32 VDD_IO 33 GND 34 DIF_6 35 DIF_6 36 VDDA 1 GNDA 2 100M_133M...