SI53119 Datasheet 19-OUTPUT PCIE GEN 3 BUFFER

Manufacturer: Silicon Laboratories

SI53119 19-output pcie gen 3 buffer by Silicon Laboratories - Datasheet Preview

Datasheet Details

Part number	SI53119
Manufacturer	Silicon Laboratories
File Size	1.29 MB
Description	19-OUTPUT PCIE GEN 3 BUFFER
Datasheet	SI53119 Datasheet

General Description

The Si53119 is a 19-output, low-power HCSL differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification.

The device is optimized for distributing refere nce clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/ Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications.

The VCO of the device is optimized to support 100 MHz and 133 MHz operation.

Overview

Si53119 19-OUTPUT PCIE GEN 3 BUFFER.

Key Features

Nineteen 0.7 V low-power, push-.
PLL or bypass mode pull HCSL PCIe Gen 3 outputs.
Spread spectrum tolerable.
100 MHz /133 MHz PLL.
1.05 to 3.3 V I/O supply voltage.
operation, supports PCIe and QPI.
PLL bandwidth SW SMBUS programming overrides the latch.
value from HW pin 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode) Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 common clock compliant).
9 selectable SMBUS addres.

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