Datasheet Summary
19-OUTPUT PCIE GEN 3 BUFFER
Features
- Nineteen 0.7 V low-power, push-
- Integrated termination resistors pull HCSL PCIe Gen 3 outputs supporting 85 transmission
- 100 MHz /133 MHz PLL lines operation, supports PCIe and
- PLL or bypass mode
- Spread spectrum tolerable
- PLL bandwidth SW SMBUS
- 1.05 to 3.3 V I/O supply voltage
- - programming overrides the latch value from HW pin
9 selectable SMBUS addresses
- -
SMBus address configurable to
- allow multiple buffers in a single control network 3.3 V supply
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel® QPI, PCIe Gen 1/Gen 2/Gen 3 mon clock pliant) voltage...