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Supertex

VN05E Datasheet Preview

VN05E Datasheet

N-Channel Enhancement-Mode Vertical DMOS Power FETs

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"§upertexinc.
I
N-Channel Enhancement-Mode
Vertical CMOS Power FETs
VN05E
Ordering Information
BVoss I
BVOGS
450V
500V
ROS(ON)
(max)
600
600
IO(ON)
(min)
150mA
150mA
TO-39
Order Number I Package
TO-92
Dice
VN0545N2
VN0545N3
VN0545ND
VN0550N2
VN0550N3
VN0550ND
Features
o Freedom from secondary breakdown
o Low power drive requirement
o Ease of paralleling
o Low CISS and fast switching speeds
o Excellent thermal stability
o Integral Source-Drain diode
o High input impedance and high gain
o Complementary N- and P-Channel devices
Applications
o Motor control
o Converters
o Amplifiers
o Switches
o Power supply circuits
o Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
Advanced CMOS Technology
These enhancement-mode (normally-off) power transistors util-
ize a vertical DMOS structure and Supertex's well-proven silicon-
gate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally-
induced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break-
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.
..
Package Options
(Notes 1 and 2)
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"
*Distance of 1.6 mm from case for 10 seconds.
±20V
8-51
TO·39
TO·92
Note 1: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.




Supertex

VN05E Datasheet Preview

VN05E Datasheet

N-Channel Enhancement-Mode Vertical DMOS Power FETs

No Preview Available !

Thermal Characteristics
" , ,"
Package
10 (cOntinuous)~
It;> (p!:,lsed)'
TO·39
100mA
TO·92
50mA
*ID (continuous) is limited by max rated Tj'
300mA
250mA
Power Dissipation
@Tc =25°C '
6W
lW
9jc
°CIW
20
125
911
°C/W
125
170
VNG5E
.
'DR 'DR\I
100mA 300mA
50mA 250mA
Electrical Characteristics (@ 25°C unless otherwise specified)
(Notes 1 and 2)
Symbol
BVDSS
Parameter
Min Typ Max Unit
Conditions
Orain-to-Source
Breakdown Voltage
VN0550
VN0545
500
450
V VGS = 0,10 = lmA
VGS(th)
Gate Threshold Voltage
2 4V
6VGS(th) Change in VGS(th) with Temperature
-3.8 -5
mVtC
IGSS
Gate Body Leakage
100 nA
lOSS
Zero Gate Voltage Orain Current
r -10 -
1000
/LA
10(ON)
ON-State Orain Current
100
150 200
mA
ROS(ON)
6 ROS(ON)
Static Orain-to-Source
ON-State Resistance
Change in ROS(ON) with Temperature
50
45 60
n
1 1.7 %tc
GFS Forward Transconductance
50 75
mU
CISS
Input Capacitance
45 55
COSS
Common Source Output Capacitance
8 10 pF
CRSS
Reverse Transfer Capacitance
25
td(ON)
Turn-ON Oelay Time
35
tr
td(OFF)
Rise Time
Turn-OFF Oelay Time
3 5 ns
35
tf
VSO
trr
Fall Time
Oiode Forward Voltage Orop
Reverse Recovery Time
35
0.8
300
V
ns
Note 1: All D,C, parameters 100% tested at 25'C unless otherwise stated, (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A,C, parameters sample tested,
VGS = VDS, 10 = lmA
VGS = VOS, 10 = lmA
VGS - ±20V, VOS - 0
VGS - O. VOS - Max Rating
VGS = 0, VOS = 0.8 Max Rating
TA = 125'C
VGS = 5V. VOS = 25V
VGS = 10V. VOS = 25V
VGS - 5V, 10 - 50mA
VGS = 10V, 10 =50mA
VGS = 10V, 10 = 50mA
VOS = 25V, 10 = SOmA
VGS = 0, VOS = 25V
f = 1 MHz
VOO = 25V
10 = 50mA
RS = 50n
VGS - O. ISO - 0.5A
VGS - 0, ISO - 0.5A
Switching Waveforms and Test Circuit
INPUT
OUTPUT
tION)
tdlON) tr
10%
tdIOFF) tf
r -;;:;:s; --,
II GENERATOR
1-~-_oSCOPE
I
\~I~+---~
D.U.T,
II
:I
IL _____ JI -=
8·52


Part Number VN05E
Description N-Channel Enhancement-Mode Vertical DMOS Power FETs
Maker Supertex
Total Page 2 Pages
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