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Supertex

VN4012 Datasheet Preview

VN4012 Datasheet

N-Channel Enhancement-Mode Vertical DMOS FET

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Supertex inc.
VN4012
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
Excellent thermal stability
Integral source-drain diode
High input impedance and high gain
Applications
Motor controls
Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps, memories,
displays, bipolar transistors, etc.)
General Description
This enhancement-mode (normally-off) transistor utilizes
a vertical DMOS structure and Supertex’s well-proven,
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors and the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Part Number
Package Option
VN4012L-G
TO-92
VN4012L-G P002
Packing
1000/Bag
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
400V
12Ω
VGS(TH)
(max)
1.8V
IDSS
(min)
150mA
VN4012L-G P003
VN4012L-G P005
TO-92
2000/Reel
Pin Configuration
VN4012L-G P013
VN4012L-G P014
-G denotes a lead (Pb)-free / RoHS compliant package.
Contact factory for Wafer / Die availablity.
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
Absolute Maximum Ratings
SOURCE
DRAIN
Parameter
Value
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
BVDSS
BVDGS
±20V
Operating and storage temperature
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
GATE
TO-92
Product Marking
Si VN YY = Year Sealed
4 0 1 2 L WW = Week Sealed
YYWW
= “Green” Packaging
Typical Thermal Resistance
Package
θja
TO-92
132OC/W
Package may or may not include the following marks: Si or
TO-92
Doc.# DSFP-VN4012
B082013
Supertex inc.
www.supertex.com




Supertex

VN4012 Datasheet Preview

VN4012 Datasheet

N-Channel Enhancement-Mode Vertical DMOS FET

No Preview Available !

Thermal Characteristics
Package
(continIDuous)
TO-92
160mA
Notes:
† ID (continuous) is limited by max rated Tj .
ID
(pulsed)
650mA
Power Dissipation
@TC = 25OC
1.0W
IDR
160mA
VN4012
IDRM
650mA
Electrical Characteristics (TA = 25OC unless otherwise specified)
Sym Parameter
Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage
400 -
-
V VGS = 0V, ID = 100µA
VGS(th) Gate threshold voltage
0.6 - 1.8 V VGS = VDS, ID = 1.0mA
IGSS Gate body leakage
- - 10 nA VGS = ±20V, VDS = 0V
IDSS Zero gate voltage drain current
ID(ON) On-state drain current
--
--
0.15 0.3
1
100
-
VGS = 0V, VDS = 0.8 Max Rating
µA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
A VGS = 4.5V, VDS = 10V
RDS(ON)
Static drain-to-source on-state
resistance
- 9.5 12
- 17 30
Ω VGS = 4.5V, ID = 100mA
VGS = 4.5V, ID = 100mA, TA = 125OC
GFS Forward transductance
125 350
- mmho VDS = 15V, ID = 100mA
CISS
COSS
CRSS
Input capacitance
Common source output capacitance
Reverse transfer capacitance
- - 110
VGS = 0V,
- - 30 pF VDS = 25V,
- - 10
f = 1.0MHz
tr
td(ON)
tf
td(OFF)
Rise time
Turn-on delay time
Fall time
Turn-off delay time
- - 20
- - 20
VDD = 25V,
-
-
65
ns ID = 100mA,
RGEN = 25Ω
- - 65
VSD Diode forward voltage drop
- - 1.2 V VGS = 0V, ISD = 160mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
INPUT
0V
10%
t(ON)
90%
t(OFF)
td(ON)
tr
td(OFF)
tf
VDD
OUTPUT
0V
10%
90%
10%
90%
Pulse
Generator
RGEN
INPUT
VDD
RL
OUTPUT
D.U.T.
Doc.# DSFP-VN4012
B082013
Supertex inc.
2 www.supertex.com


Part Number VN4012
Description N-Channel Enhancement-Mode Vertical DMOS FET
Maker Supertex
Total Page 3 Pages
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