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Supertex

VP03E Datasheet Preview

VP03E Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

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VP03E
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss /
BVOGS
-450V
-500V
ROS(ON)
(max)
7.50
7.50
IO(ON)
(min)
-1A
-1A
TO-3
VP0345Nl
VP0350Nl
Order Number / Package
TO-39
TO-220
VP0345N2
VP0345N5
VP0350N2
VP0350N5
CICE
VP0345ND
VP0350ND
Features
o Freedom from secondary breakdown
o Low power drive requirement
o Ease of paralleling
o Low C1SS and fast switching speeds
o Excellent thermal stability
o Integral Source-Drain diode
o High input impedance and high gain
o Complementary N- and P-Channel devices
Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors util-
ize a vertical DMOS structure and Supertex's well-proven silicon-
gate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally-
induced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break-
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.
~
Applications
o Motor control
o Convertors
o Amplifiers
o Switches
o Power supply circuits
o Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
Package Options
(Notes 1 and 2)
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature'
*Distance of 1.6 mm from case for 10 seconds.
±20V
9-25
TO·39
TO·220
Note 1: See Package Outline section for discrete pinouts,
Note 2: See Array section for quad pinouts.




Supertex

VP03E Datasheet Preview

VP03E Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

No Preview Available !

Thermal Characteristics
Package
10 (continuous)'
10 (pulsed)'
TO-3
TO-39
-1.5A
-0.4A
TO-220
-1.0A
• Ie (continuous) Is limited by max rated Tj'
-3.0A
-3.0A
-S.OA
Power Dissipation
@Tc=25°C
100W
6W
50W
9)e
°C/W
1.25
20.8
2.5
9)8
°CIW
30
125
40
lOR
-1.5A
-0.4A
-I.OA
VP03E
10RM'
-3.0A
:3.0A
-3.0A
Electrical Characteristics (@ 25°C unless otherwise specified)
(Notes I and 2)
Symbol
BVess
VGS(lh)
!'..VGS(lh)
IGSS
less
Parameter
Min Typ Max Unit
Drain-to-Source
Breakdown Voltage
I VP0350
I VP0345
-500
-450
V
Gate Threshold Voltage
-2.5 -4.5 V
Change in VGS(lh) with Temperature
-4.8 -6.0 mV/oC
Gate Body Leakage
-100 nA
Zero Gate Voltage Drain Current
-200 itA
-2 mA
le(ON)
ON-State Drain Current
-0.75
-1.0 -2.5
A
ReS(ON)
Static Drain-to-Source
ON-State Resistance
6.0
5.5 7.5
0
!'..ReS(ONL Change in Res(ON) with Temperature
0.7 1.2 %/"C
GFS Forward Transconductance
0.25 0.75
U
CISS Input CapaCitance
550 700
Coss
Common Source Output Capacitance
90 120
pF
CRSS
Reverse Transfer Capacitance
20 50
tdON Turn-ON Delay Time
II 30
tr
td OFF
Rise Time
Turn-OFF Delay Time
II 30
70 100
ns
~ Fall Time
22 30
Vse Diode Forward Voltage Drop
-1.0 -1.3
V
trr Reverse Recovery Time
550 ns
Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300)!s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.
Conditions
VGS= 0, Ie =-IOmA
VGS = Yes' Ie = -IOmA
VGS = Yes' Ie = -IOmA
VGS = ±20V, Ves = 0
VGS = 0, Ves = Max Rating
VGS = 0, Ves = 0.8 Max Rating
TA = 125°C
VGS = -5V, Ves = -25V
VGs=-IOV, Ves =-25V
VGS = -5V, Ie = -0.25A
VGS = -IOV, Ie = -0.25A
VGS = -IOV, le= -0.25A
Ves = -25V, Ie = -0.5A
VGS = 0, Ves = -25V
f= I MHz
Vee = -25V
Ie = -0.5A
Rs =500
VGS = 0, Ise = -0.25A
VGS = 0, Ise = -0.25A
Switching Waveforms and Test Circuit
td(ON)
Output - - - - - - . I
10%
1-- - -pulsE - --I
: GENERATOR
I
j-,..~__IJSCOPE
I
V-~~--~~
D.U.T.
I
I
I
I
I
LI ____-:______II
9-26


Part Number VP03E
Description P-Channel Enhancement-Mode Vertical DMOS FETs
Maker Supertex
Total Page 4 Pages
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