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Supertex

VP1008 Datasheet Preview

VP1008 Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

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IIl1
"-11
§
u
per
tex
inc.
VP0808
VP1008
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVoss I
BVOGS
-80V
-100V
ROSION)
(max)
5f.!
5f.!
JOlON)
(min)
-UA
-1.1A
Features
D Freedom from secondary breakdown
D Low power drive requirement
D Ease of paralleling
D Low CISS and fast switching speeds
D Excellent thermal stability
D Integral Source-Drain diode
D High input impedance and high gain
D Complementary N- and P-Channel devices
Order Number I Package
TO-39
TO-92
VP0808B
VP1008B
VP0808L
VP1008L
Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors util-
ize a vertical DMOS structure and Supertex's well-proven silicon-
gate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally-
induced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break-
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.
..I
I
,
Applications
D Motor control
D Converters
D Amplifiers
D Switches
D Power supply circuits
D Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature'
'Dlstance of 1.6 mm from case for 10 seconds.
Package Options
(Note 1)
i
TO·39
TO·92
±40V
Note 1: See Package Outline section for discrete pinouts.
9-47




Supertex

VP1008 Datasheet Preview

VP1008 Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

No Preview Available !

Thermal Characteristics
Package
'0 (continuous)' .
TO-39
-O.BBA
TO-92
-0.21A
*10 (conlinuous) is limiled by max raled TI'
10 (pulsed)
-3A
-3A
Power Olssipation
6.2SW
OAW
OJ.
°C/W
170
312.S
°Je
°CIW
20
41
VP0808/vP1008
Electrical Characteristics (@ 25°C unless otherwise specified)
(Notes 1 and 2)
Symbol
BVDSS
VGS(th)
IGSS
IDSS
Parameter
Drain-to-Source
Breakdown Voltage
Gate Threshold Voltage
Gate Body Leakage
Zero Gate Voltage Drain Current
Min
VP100B
-100
VPOBOB ~BO
-2
TYP Max Unit
V
-4.S
100
-10
I---
-SOO
V
nA
",A
ID(ON)
ON-State Drain Current
-1.1
A
RDS(ON)
Static Drail1-to-Source
ON-State Resistance
n
S
GFS
Forward Transconductance
200
mU
CISS
Input Capacitance
1S0
COSS
Common Source Output Capacitance
60 pF
CRSS
Reverse Transler Capacitance
2S
td(ON)
Turn-ON Delay Time
10
Ir
td(OFF)
Rise Time
Turn-OFF Delay Time
10
ns
10
tf Fall Time
10
VSD
Diode Forward Voltage Drop
VP1008
1.2
V
VPOBOB
1.2
Note I: All D.C. parameters 100% tesled at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.
Conditions
ID = -1O",A, VGS = 0
VGS = VDS, ID = -1mA
VGS = 30V, VDS = 0
VGS = OV, VDS = Max Rating
VGS = OV, VDS = Max Rating
TA = 12S'C
VGS = -10V, VDS .. 2 VDS(ON)
VGS = -10V, ID = -1A
VDS .. 2 VDS(ON), ID = -O.SA
VGS = 0, VDS = 2SV
1= 1MHz
VDD = -2SV, ID = -O.SA
RS = son
ISD = 0.21A, VGS = 0
ISD = 0.9A, VGS = 0
Switching Waveforms and Test Circuit
INPUT
OUTPUT
r - ;;L-;; --,
I GENERATOR
I
1-....,.,,---0 SCOPE
I \~I~+-~~
O.U.T.
II
:I
IL _____ JI
9-48


Part Number VP1008
Description P-Channel Enhancement-Mode Vertical DMOS FETs
Maker Supertex
Total Page 2 Pages
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