THC63LVD104A Datasheet | THine Electronics

THC63LVD104A Rev.1.0 90MHz 30Bits COLOR LVDS Receiver THine General Description The THC63LVD104A receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to WXGA resolutions. The THC63LVD104A converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falling edge clock for convenient with a variety of LCD panel controllers.At a transmit clock frequency of 90MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 630Mbps per LVDS channel.Using a 90MHz clock, the data throughput is 394Mbytes per second. Features - Wide dot clock range: 8-90MHz suited for NTSC, VGA, SVGA, XGA, and WXGA - PLL requires no external ponents - 50% output clock duty cycle - TTL clock edge programmable - Power down mode - Low power single 3.3V CMOS design - 64pin TQFP - Backward patible with THC63LVDF64x (18bits) /...