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THine Electronics

THC63LVD104A Datasheet Preview

THC63LVD104A Datasheet

90MHz 30Bits COLOR LVDS Receiver

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THC63LVD104A Rev.1.0
THC63LVD104A
90MHz 30Bits COLOR LVDS Receiver
THine
General Description
The THC63LVD104A receiver is designed to support
pixel data transmission between Host and Flat Panel
Display from NTSC up to WXGA resolutions. The
THC63LVD104A converts the LVDS data streams back
into 35bits of CMOS/TTL data with rising edge or fall-
ing edge clock for convenient with a variety of LCD
panel controllers.At a transmit clock frequency of
90MHz, 30bits of RGB data and 5bits of timing and
control data (HSYNC,VSYNC,DE,CNTL1,CNTL2)
are transmitted at an effective rate of 630Mbps per
LVDS channel.Using a 90MHz clock, the data through-
put is 394Mbytes per second.
Features
Wide dot clock range: 8-90MHz suited for NTSC,
VGA, SVGA, XGA, and WXGA
PLL requires no external components
50% output clock duty cycle
TTL clock edge programmable
Power down mode
Low power single 3.3V CMOS design
64pin TQFP
Backward compatible with THC63LVDF64x
(18bits) / F84x(24bits)
Block Diagram
LVDS INPUT
RA+/-
RB+/-
RC+/-
RD+/-
RE+/-
RCLK+/-
(8 to90MHz)
CMOS/TTL INPUT
TEST
PD
OE
R/F
PLL
Copyright 2003 THine Electronics, Inc. All rights reserved
1
CMOS/TTL OUTPUT
7 RA6-RA0
7 RB6-RB0
7 RC6-RC0
7 RD6-RD0
7 RE6-RE0
CLKOUT
THine Electronics, Inc.




THine Electronics

THC63LVD104A Datasheet Preview

THC63LVD104A Datasheet

90MHz 30Bits COLOR LVDS Receiver

No Preview Available !

THC63LVD104A Rev.1.0
Pin Out
RA-
RA+
RB-
RB+
LVCC
RC-
RC+
RCLK-
RCLK+
LGND
RD-
RD+
RE-
RE+
PGND
PVCC
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
THine
32 RB6
31 CLKOUT
30 GND
29 RC0
28 RC1
27 RC2
26 RC3
25 RC4
24 RC5
23 VCC
22 RC6
21 RD0
20 RD1
19 RD2
18 RD3
17 RD4
Copyright 2003 THine Electronics, Inc. All rights reserved
2
THine Electronics, Inc.


Part Number THC63LVD104A
Description 90MHz 30Bits COLOR LVDS Receiver
Maker THine Electronics
Total Page 13 Pages
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