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TC511000P-10 - DRAM

Download the TC511000P-10 datasheet PDF. This datasheet also covers the TC511000P-85 variant, as both devices belong to the same dram family and are provided as variant models within a single manufacturer datasheet.

Description

The TC5llOOOP/J/Z is the ne~v generation dynamic RAN organized 1,048,576 words by 1 bit.

Features

  • include single power supply of 5V±10% tolerance" direct interfacing capability with high performance logic families such as Schottky TTL. IJTest Mode" function is implemented from Ilevision C.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC511000P-85-Toshiba.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TOSHIBA MOS MEMORY PRODUCT 1,048,576 WORDS X 1 BIT DYNAMIC RAM SILICON GATE CMOS DESCRIPTION TC511000P/J/Z-85, TC511000P/J/Z-l0 TC511000P/J/Z-12 The TC5llOOOP/J/Z is the ne~v generation dynamic RAN organized 1,048,576 words by 1 bit. The TC5llOOOP/J/Z utilizes TOSHIBA's CHOS Silicon gate process technology as well as ad- vanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC5llOOOP/J/Z to be packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.
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