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TC74ACT112P Key Features

  • High speed: fmax = 175 MHz (typ.) at VCC = 5 V
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
  • patible with TTL outputs: VIL = 0.8 V (max)
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
  • Balanced propagation delays: tpLH ∼- tpHL
  • Pin and function patible with 74F112

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TC74ACT112P Description

TC74ACT112P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT112P, TC74ACT112F Dual J-K Flip Flop with Preset and Clear The TC74ACT112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This...