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TC74ACT174F - Hex D-Type Flip-Flop

Download the TC74ACT174F datasheet PDF. This datasheet also covers the TC74ACT174P variant, as both devices belong to the same hex d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 155 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74F174 Pin Assignment TC74ACT174P TC74ACT174F Weight DIP16-P-300-2.54A SOP16-P-300-1.27.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74ACT174P-Toshiba.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74ACT174P Hex D-Type Flip-Flop
TC74ACT112F Dual J-K Flip-Flop
TC74ACT112P Dual J-K Flip-Flop
TC74ACT04F Hex Inverter
TC74ACT04FT Hex Inverter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74ACT174P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT174P, TC74ACT174F Hex D-Type Flip Flop with Clear The TC74ACT174 is an advanced high speed CMOS HEX D-TYPE FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLR input is held low, the Q output are in the low logic level independent of the other inputs.