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TC74ACT257F - 2-Channel Multiplexer

Download the TC74ACT257F datasheet PDF. This datasheet also covers the TC74ACT257P variant, as both devices belong to the same 2-channel multiplexer family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: tpd = 5.8 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74F257 Pin Assignment TC74ACT257P TC74ACT257F Weight DIP16-P-300-2.54A SOP16-P-300-1.27A.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74ACT257P-Toshiba.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Toshiba

Part Number Description
TC74ACT257P 2-Channel Multiplexer
TC74ACT280F 9-Bit Parity Generator/Checker
TC74ACT280P 9-Bit Parity Generator/Checker
TC74ACT299F 8-Bit PIPO Shift Register
TC74ACT299P 8-Bit PIPO Shift Register
TC74ACT04F Hex Inverter
TC74ACT04FT Hex Inverter
TC74ACT04P Hex Inverter
TC74ACT08F Quad 2-Input AND Gate
TC74ACT08P Quad 2-Input AND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74ACT257P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT257P, TC74ACT257F 2-Channel Multiplexer (3-state) The TC74ACT257 is an advanced high speed CMOS MULTIPLEXER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieve the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL or NMOS and CMOS output voltage levels. Each is composed of four independent 2-channel multiplexers with common SELECT and OUTPUT ENABLE ( OE ). If OE is set low, the outputs are held in a high-impedance state. When SELECT is set low, “A” data inputs are enabled.