UR5595 Datasheet | Unisonic Technologies

UNISONIC TECHNOLOGIES CO., LTD UR5595 DDR TERMINATION REGULATOR CMOS IC - DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the UR5595 can provide superior load regulation. The UR5595 provides a VREF output as the reference for the application of the chipset and DIMMs. The output, VTT, is...