* Power regulating with driving and sinking capability * Low output voltage offset * No external resistors required * Low external component count * Linear topology * Lo.
the AVIN and PVIN can be short together at 2.5V to eliminate the need for bypassing capacitors for the two supply pins .
The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent res.
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