ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3 -7 7ns 45ns CL=2 CL=3 V28S20D 20ns 5.4ns 63ns 85mA 85mA 85mA 1mA P2V28S20/30/40ATP -75 -8 10ns 7.5ns .

P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and output.

P2V28S30ATP-75

P2V28S30ATP-8

P2V28S20ATP-7

P2V28S20ATP-75

P2V28S20ATP-8

P2V28S20DTP-7

P2V28S40ATP-7

P2V28S40ATP-75

P2V28S40ATP-8

P2V2FB

P2V2FB1

P2V2FB2

P2V0FB