VG36643241BT-10 Datasheet | Vanguard International Semiconductor

Description Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package. Features - Single 3.3V ( ± 0.3V ) power supply - High speed clock cycle time : 8/10 for LVTTL - High speed clock cycle time : 8/10 for SSTL - 3 - Fully synchronous with all signals referenced to a positive clock edge - Programmable CAS Iatency (2,3) - Programmable burst length (1,2,4,8,& Full page) - Programmable wrap sequence (Sequential/Interleave) - Automatic precharge and controlled precharge - Auto refresh and self refresh modes - Dual Internal banks controlled by A11 (Bank select) for VG36643211(2) - Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2) - Each Banks can operate simultaneously and independently - LVTTL patible I/O interface for VG36643211 and VG36643241 - SSTL - 3 patible I/O interface for VG36643212 and VG36643242 - Random column access in every cycle - x32 organization - Input/Output controlled by DQM0 ~ 3 - 4,096 refresh cycles/64ms - Burst termination by burst stop and precharge mand - Burst read/single write option Document : 1G5-0099 Rev.1 Page 1 Pin Configuration VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS NC A11/BA NC A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic...