SI3430DY Datasheet | Vishay

DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a mercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71524 S-50383Rev. B, 21-Mar-05 .vishay. 1 Datasheet pdf - http://..net/ .Data Sheet.co.kr SPICE Device Model Si3430DY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea b Symbol VGS(th) ID(on) r DS(on) gfs VSD Test Conditions VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 2.4 A VGS = 6 V, ID = 2.3 A VDS = 15 V, ID = 2.4 A IS = 1.7 A, VGS = 0 V Typical 3 34 0.146 0.154 8.1 0.72 Unit V A Ω S V Dynamic Total Gate Chargeb Gate-Source Chargeb Gate-Drain Chargeb Turn-On Delay Time Rise Timeb Turn-Off Delay Timeb Fall Time b Qg Qgs Qgd td(on) tr td(off) tf trr IF = 1.7 A, di/dt = 100 A/µs VDD = 50 V, RL = 50 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω VDS = 50 V, VGS = 10 V, ID = 2.4 A 6.06 1.5 1.4 8 10 23 30 52 ns n C Source-Drain Reverse Recovery Time Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2% b. Guaranteed by design, not subject to production testing. .vishay....