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W332M64V-XSBX - 32Mx64 Synchronous DRAM

Datasheet Summary

Description

The 256MByte (2Gb) SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 536,870,912 bits.

Each chip is internally configured as a quad-bank DRAM with a synchronous interface.

Each of the chip’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits.

Features

  • High Frequency = 100, 125, 133MHz Package:.
  • 208 Plastic Ball Grid Array (PBGA), 13 x 22mm 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 8192 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 32M x 64 Weight: W332M64V-XSBX - 1.4.

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Datasheet Details

Part number W332M64V-XSBX
Manufacturer White Electronic Designs
File Size 334.88 KB
Description 32Mx64 Synchronous DRAM
Datasheet download datasheet W332M64V-XSBX Datasheet
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White Electronic Designs 32Mx64 Synchronous DRAM FEATURES High Frequency = 100, 125, 133MHz Package: • 208 Plastic Ball Grid Array (PBGA), 13 x 22mm 3.3V ±0.3V power supply Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 8192 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 32M x 64 Weight: W332M64V-XSBX - 1.4 grams typical W332M64V-XSBX www.DataSheet4U.com GENERAL DESCRIPTION The 256MByte (2Gb) SDRAM is a high-speed CMOS, dynamic random-access, memory using 4 chips containing 536,870,912 bits.
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