WV3EG64M64ETSU-D3 unbuffered equivalent, 512mb - 64mx64 ddr sdram unbuffered.
Double-data-rate architecture PC2700 @ CL 2.5 Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable .
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OPERATING FREQUENCIES
DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3
August 2005 Rev. 1
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